Static random access memories (SRAM) are commonly used in integrated circuits. Embedded SRAM is particularly popular in high speed communication, image processing and system on chip (SOC) applications. SRAM cells have the advantageous feature of holding data without requiring a refresh. Typically, a SRAM cell includes two pass-gate transistors, through which a bit can be read from or written into the SRAM cell. This type of SRAM cell is referred to as a single port SRAM cell. Another type of SRAM cell is referred to as dual port SRAM cell, which includes four pass-gate transistors.
FIG. 1 illustrates an exemplary circuit diagram of a prior art eight-transistor dual port SRAM cell, which includes pull-up transistors PU-1 and PU-2 and pull-down transistors PD-1 and PD-2. Pass-gate transistors PG-1 and PG-3 form a first port (port-A) of the dual port SRAM cell. Pass-gate transistors PG-2 and PG-4 form a second port (port-B) of the dual port SRAM cell. The gates of pass-gate transistors PG-1 and PG-3 are controlled by word-line port-A WL, while the gates of pass-gate transistors PG-2 and PG-4 are controlled by word-line port-B WL. A latch formed of pull-up transistors PU-1 and PU-2 and pull-down transistors PD-1 and PD-2 stores a bit. The stored bit can be read through port-A using bit lines port-A BL and port-A BLB, or through port-B using bit lines port-B BL and port-B BLB. Conversely, a bit can be written into the SRAM cell through either port-A or port-B.
With two ports, the bit stored in the SRAM cell can be read from port-A and port-B simultaneously. This allows for parallel operations by different applications. Moreover, if a first SRAM cell and a second SRAM cell are in a same column or a same row, a read operation to the first SRAM cell can also be performed simultaneously with a write operation on the second SRAM cell.
Conventionally, to support parallel operations, in which two ports may be at the “on” state at the same time, the pull-down transistors PD-1 and PD-2 each need to sustain twice the drive current of each of the pass-gate transistors PG-1 through PG-4. Accordingly, in conventional designs, pull-down transistors PD-1 and PD-2 were designed twice as wide as pass-gate transistors PG-1 through PG-4. Typically, L- or T-shaped active regions are used to provide this uneven device sizing. FIG. 2 illustrates a conventional layout of transistors PG-1 and PD-1 in a common active region. The dotted region is an active region, and shaded regions are gate polysilicon lines. The active region is L-shaped, with a wide portion for forming pull-down transistor PD-1 being twice as wide or even greater than a narrow portion for forming pass-gate transistor PG-1. Due to optical effects, the intersection region between the wide portion and the narrow portion is rounded. If a misalignment occurs, and the gate poly of pass-gate transistor PG-1 is moved up, the actual gate width of pass-gate transistor PG-1 will be greater than desired. Accordingly, a mismatching occurs between pass-gate transistor PG-1 and pass-gate transistors PG-2 through PG-4, which in turn affects the SRAM cell performance.
An additional problem is the current crowding at the intersection region. In the intersection region, the currents are not evenly distributed. Therefore, some portions of the pull-down devices PD-1 and PD-2 may have greater current densities than other portions. Junction leakage is also a concern.
Accordingly, an improved SRAM cell that may incorporate dual ports thereof to take advantage of the benefits associated with the parallel operations is desired.